The present invention relates to a configuration of a decimation filter called xe2x80x9csinc filterxe2x80x9d to process high-speed transmitting pulse signals.
Heretofore, configurations of a decimation filter including superconducting circuits have been described in various literature as follows. First to fourth examples of the prior art are described respectively in literature: J. X. Lin et al., Design of SFQ-Counting Analog-to-Digital Converter, IEEE Transactions on Applied Superconductivity, vol. 5, no. 2, June 1995, pp. 2252-2259; Q. P. Herr et al., High Speed Testing of a Four-Bit RSFQ Decimation Digital Filter, IEEE Transactions on Applied Superconductivity, vol. 7, no. 2, June 1997, pp. 2975-2978; Y. P. Xie et al., Decimation Filter with Novel MVTL XOR Gate, IEEE Transactions on Applied Superconductivity, vol. 7, no. 2, June 1997, pp. 2480-2483; K. K. Likharev et al., RSFQ Logic/Memory Family: A New Josephson-Junction Technology for Sub-Terahertz-Clock-Frequency Digital Systems, IEEE Transactions on Applied Superconductivity, vol. 1, no. 1, March 1991, PP. 3-28; and Dijkstra et al., On The Use Of Modulo Arithmetic Comb Filters In Sigma Delta Modulators, IEEE Proc. ICASSP ""88, April 1988, pp. 457-460.
As shown in FIG. 6A of the first example, a sinc filter which is one type of decimation filters receives input signal Xi transmitted with a period of one clock time and produces a sum with respect to subscript i assigned according to the clock signal as a unit of time. The sinc filter repeatedly executes the operation above.
When the operation is repeated k times a k-th order sinc filter is obtained. The prior art example shows a second order sinc filter. The filter of FIG. 6A includes a delay unit shown as xe2x80x9cD cellxe2x80x9d, a non-destructive toggle flip-flop (TFF) circuit indicated as xe2x80x9cNT cellxe2x80x9d, a destructive toggle flip-flop circuit indicated as xe2x80x9cT1 cellxe2x80x9d, and a pulse splitter in which one signal line branches to two signal lines. This example employs a double-integration algorithm in which input signal Xi is summed up with respect to subscript i to attain vn, and then the value of vn is again summed up with respect to subscript n to obtain yi. That is, the summation is conducted twice to perform a filter operation.
The destructive toggle flip-flop circuits (T1 cells) are connected in series to each other to form a counter of which a count value is reset to zero by a readout signal. This configuration further includes non-destructive toggle flip-flop circuits (NT cells). Since this prior art example includes various constituent elements such as T1 cells and NT cells, the circuit configuration is complicated, which hinders a high-speed operation. To achieve a higher operation, the circuit must be much more simplified in configuration.
As can be seen from expression (1) of the second prior art example, a decimation filter can be implemented as follows. An appropriate coefficient ci is multiplied by input signal Xi and then a product from the multiplication is summed up with respect to subscript i assigned according to a clock signal as a unit of time. Therefore, various decimation filters can be implemented only by selecting appropriate coefficients ci. Therefore, this method is advantageously used for general purposes.
However, as shown in FIG. 1 of the literature of the second prior art, the circuit configuration includes various circuit components such as a coefficient memory unit, a control unit, and an input/output interface. Namely, the circuit configuration is complex and of a large size, which hinders a high-speed operation of the circuit.
As shown in FIG. 5 of the literature of the third prior art example, this example is a second order sinc filter including two accumulators, one down-sampler, two differentiators. This system includes a reduced number of types of circuit components and hence has an advantage of a simple circuit construction. However, the accumulator includes a feedback section and conducts an arithmetic sum. Therefore it is required to perform a modulo arithmetic. Moreover, two accumulators are connected in cascade to each other that causes a large value obtained thereof and there arises a problem that the circuit size is also increased. Such large size of the circuit configuration hinders a high-speed operation.
It is therefore an object of the present invention to provide a decimation filter not including a feedback circuit which leads to undesired increase in the numeric value or undesired overflow.
Another object of the present invention is to provide a decimation filter which includes a reduced number of kinds of circuit components suitable for a high-speed operation and which does not include a feedback section.
To achieve the objects above in accordance with the present invention, there is provided a decimation filter including delay units for sequentially delaying an input signal one clock and for producing a plurality of delayed signals, adders for sequentially adding the delayed signals to each other and for producing total signal, and a counter connected to outputs from said adders for counting pulses of the total signals from said adders.
The adders may include a plurality of confluence buffers connected in series to each other for merging a plurality of signal lines into one signal line. The counter each can count pulses of the total signals during a period of time which is an integral multiple of a period of one clock signal. The counter may include a plurality of frequency multiplier (xc3x971/2) circuits connected in series to each other.
According to one aspect of the present invention, the counter can produce a count value according to a readout signal inputted thereto during a period of time which is an integral multiple of a period of a clock signal and can be thereby set to a reset state.
The objects and features of the present invention will become more apparent from the consideration of the following detailed description taken in conjunction with the accompanying drawings.